Various techniques are known in the art for increasing the effective rate at which data can be transmitted over a bus or, equivalently, for reducing the number of bus lines needed to sustain a given data bandwidth. Citron et al. describe one such method, based on data compression, in “Creating a Wider Bus Using Caching Techniques,” Proceedings of the First IEEE Symposium on High-Performance Computer Architecture (January, 1995), pages 90–99, which is incorporated herein by reference. Rather than transmitting an entire data word over a bus, data compaction is first performed by caching the high-order bits of the word in a table, and sending an index to the table over the bus along with the low-order bits. A coherent table at the receiving end expands the word into its original form. Compaction/expansion units can be placed between a processor and memory, between a processor and a local bus, and between devices that access the system bus.
Data compression may be used in enhancing the performance of cache memories. For example, Yang et al. describe a method for storing data in compressed form so as to reduce the power consumed by a cache memory, in “Frequent Value Compression in Data Caches,” Proceedings of the 33rd International Symposium on Microarchitecture (December, 2000), pages 258–275, which is incorporated herein by reference. The authors use a data compression scheme that is based on encoding a small number of values that appear frequently during memory accesses, while preserving the ability to randomly access individual data items.
As another example, U.S. Pat. No. 6,044,437, to Reinders, whose disclosure is incorporated herein by reference, describes a method for reducing the number of cache line data transfers among components of a computer system based on generating and transferring redundancy bits between levels of a cache memory hierarchy. Redundancy logic is provided to detect occurrences of redundant data strings in a given cache line, to generate and transfer redundancy bits when such strings occur, and to decode the redundancy bits at the destination. If redundant data strings occur in a cache line, the transfer of one or more portions of the cache line can thus be canceled. This method is said to reduce the amount of bus traffic and increase overall system performance.